1. Field of the Invention
The present invention relates to a semiconductor memory device having a self-refresh function and more particularly, to an improvement of a background refresh system.
2. Description of the Prior Art
As a semiconductor memory device having a self-refresh function, a virtually static random access memory (referred to as VSRAM hereinafter) has been known. In the VSRAM, a static random access memory (static RAM) is substantially achieved using memory cells used for a dynamic random access memeory (dynamic RAM). More specifically, each of the memory cells in the VSRAM comprises a single MOSFET (metal oxide semiconductor field effect transistor) and a single capacitor, and a refresh operation for the memory cell is performed on a chip. Consequently, the user need not prepare a circuit for the refresh operation and the user is relieved of the burden.
FIG. 1 is a block diagram showing a conventional example of such a VSRAM. The VSRAM is described in, for example, an article, by K. Nogami et al., entitled "1-M bit Virtually Static RAM", IEEE J. Solid-State Circuits, Vol. SC-21, No. 5, October 1986 and an article by T. Sakurai et al., "A 1Mb virtually SRAM", IEEE 1986 International Solid-State Circuits Conference, February 1986, Digest of Technical Papers, pp. 252-253 and p. 364.
Referring to FIG. 1, each of memory cell arrays 1 comprise a plurality of memory cells arranged in a plurality of rows and columns. Word lines are provided corresponding to rows in the memory cell array 1, respectively and bit lines are provided corresponding to columns in the memory cell array 1, respectively. When a normal access, that is, an access for reading or writing data is made to the memory cells, a normal access request signal ACSREQ is applied to an arbiter circuit 11 from a control circuit 13 and a row address signal RA and a column address signal CA are applied to a row address buffer 7 and a column address buffer 12, respectively, from an exterior at timing as shown in FIG. 2. The row address signal RA buffered by the row address buffer 7 is applied to an address multiplexer 8. When a refresh operation is not performed, the arbiter circuit 11 is responsive to the normal access request signal ACSREQ for switching the address multiplexer 8 such that the row address signal RA is applied to a row decoder 3. The row decoder 3 decodes the row address signal RA, selects a single word line in the memory cell array 1 and raises a potential on the word line to a high level (see FIG. 2). Consequently, data are read out to corresponding bit lines from memory cells in one row connected to the selected word line. The data on the bit lines are detected and amplified by sense amplifiers included in the group 2 of sense amplifiers, respectively. As a result, potentials on the bit lines attain a high level or a low level as represented by D in FIG. 2.
On the other hand, the column address signal CA buffered by the column address buffer 12 is applied to a column decoder 4 through a timing generator 6. The column decoder 4 decodes the column address signal CA and selects one column in the memory cell array 1. Data on a bit line corresponding to the column is held once in a buffer register 5 and then, outputted to an input/output pin 15 through an input/output buffer 14 as effective data. The buffer register 5 is provided to release memory cells earlier from a normal access by transferring data in the memory cells to the buffer register 5 thereby to increase the refreshable time period.
The refresh operation of the VSRAM is performed in the time period during which the word lines, the memory cells, the group 2 of sense amplifiers and the like are not employed by the normal access. Such a time period is, for example, the address skew time period, the address decoding time period and the output circuit driving time period in the normal access. The refresh operation must be performed before data stored in each of the memory cells disappears with the lapse of time. A refresh timer 10 measures the time period corresponding to the time period during which data stored in the memory cell can be held, and applies a refresh request signal REFREQ to the arbiter circuit 11 and a refresh address counter 9 when a refresh operation is required. The refresh address counter 9 is responsive to the refresh request signal REFREQ for applying a refresh address signal RFA corresponding to a row to be refreshed in the memory cell array 1 to the address multiplexer 8. When the memory cell is released from the normal access, the arbiter circuit 11 switches the address multiplexer 8 such that the refresh address signal RFA is applied to the row decoder 3. The row decoder 3 is responsive to the refresh address signal RFA for selecting a single word line in the memory cell array 1 and raising a potential on the word line to a high level as shown in FIG. 2. Data are read out to corresponding bit lines from memory cells in one row connected to the selected word line, respectively, and detected and amplified by the sense amplifiers included in the group 2 of sense amplifiers, respectively. Consequently, potentials on the bit lines attain a high level or a low level as represented by RF in FIG. 2. A potential on the word line falls to a low level, so that the data on the bit lines are held again in the memory cells. In the above described manner, a refresh operation of memory cells is performed.
On the other hand, if the refresh request signal REFREQ is applied from the refresh timer 10 when a normal access operation is performed for memory cells, the arbiter circuit 11 delays a refresh operation until the normal access operation is completed. The arbiter circuit 11 enables the refresh operation after the memory cells are released from the normal access. On the other hand, if the normal access request signal ACSREQ is applied from the control circuit 13 when a refresh operation is performed, the arbiter circuit 11 enables a normal access operation after the memory cells are released from the refresh operation. In this case, considering that the refresh operation and the normal access operation conflicts, the refresh operation must be performed before the data in the memory cells disappear.
The conventional VSRAM has the above described structure. Thus, if a normal access request and a refresh request conflict, the other operation must be delayed until memory cells are released from one operation. Particularly, if a normal access operation is required during a refresh operation, the normal access operation enters the waiting state, so that the access time is longer by the refresh time period. The refresh time period is the sum of the time period required for raising the potentials on the word lines by the row decoder 3 and the time period required for amplification by the sense amplifiers.
On the other hand, if and when the above described conflict does not occur, the access time is relatively shorter. Thus, the access time is substantially changed depending on the presence or absence of conflict, so that the access time can not be made uniform.
A technique is considered in which a refresh operation is performed until a decoding operation for the next normal access is started after data is transferred to the buffer register 5. However, in this case, the time period for the refresh operation must be ensured in advance from one normal access to the next normal access. Consequently, viewed from the exterior of the VSRAM, it means that the access time in the normal access becomes substantially longer. Accordingly, the cycle time is longer as a whole. Meanwhile, in a semiconductor memory device other than the semiconductor memory device of a self-refresh type, an approach of adjusting timing outside the semiconductor memory device is taken. However, in the self-refresh type semiconductor memory device, such an approach can not be taken.
Thus, in the conventional self-refresh type semiconductor memory device, since the access time becomes longer when a normal access operation and a refresh operation conflict, the access time becomes nonuniform. In order to avoid the nonuniformity, the access time becomes longer when conflict does not occur. Consequently, high speed access by reducing the access time in the normal access and thus, the cycle time uniformly, can not be achieved.